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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . c o m m o n s i n g l e p w m c o n t r o l l e r w i t h m u l t i f o r m s u p p l y v o l t a g e a p w 8 7 2 4 f e a t u r e s g e n e r a l d e s c r i p t i o n a d j u s t a b l e o u t p u t v o l t a g e f r o m + 0 . 6 v t o + 5 . 0 v - 0 . 6 v r e f e r e n c e v o l t a g e - + 0 . 6 % a c c u r a c y o p e r a t e s f r o m a n i n p u t b a t t e r y v o l t a g e r a n g e o f + 3 v t o + 2 5 v multiform purpose input voltage collocation - v cc =5v / v in =8~19v for nb application - v cc =5~12v / v in =5~12v for table pc application remote feedback sense for excellent output voltage regulation p o w e r - o n - r e s e t m o n i t o r i n g o n v c c p i n e x c e l l e n t l i n e a n d l o a d t r a n s i e n t r e s p o n s e s ultrasonic operation eliminated audio noise p f m m o d e f o r i n c r e a s e d l i g h t l o a d e f f i c i e n c y 3 0 0 k h z c o n s t a n t p w m s w i t c h i n g f r e q u e n c y i n t e g r a t e d m o s f e t d r i v e r s integrated bootstrap forward p-ch mosfet a d j u s t a b l e i n t e g r a t e d s o f t - s t a r t power good monitoring 70% under-voltage protection 125% over-voltage protection adjustable current-limit protection - using sense low-side mosfet?s rds(on) over-temperature protection tdfn3x3-10 package lead free and green devices available (rohs compliant) a p p l i c a t i o n s n o t e b o o k t a b l e p c h a n d - h e l d p o r t a b l e a i o p c w i d e i n p u t d c / d c r e g u l a t o r s t h e a p w 8 7 2 4 i s a s i n g l e - p h a s e , c o n s t a n t o n - t i m e , s y n - c h r o n o u s p w m c o n t r o l l e r , w h i c h d r i v e s n - c h a n n e l m o s f e t s . t h e a p w 8 7 2 4 s t e p s d o w n h i g h v o l t a g e t o g e n e r a t e l o w - v o l t a g e c h i p s e t , r a m s u p p l i e s i n n o t e b o o k c o m p u t e r s o r m o t h e r b o a r d a p p l i c a t i o n s . t h e a p w 8 7 2 4 p r o v i d e s e x c e l l e n t t r a n s i e n t r e s p o n s e a n d a c c u r a t e d c v o l t a g e o u t p u t i n e i t h e r p f m o r p w m m o d e . i n p u l s e f r e q u e n c y m o d e ( p f m ) , t h e a p w 8 7 2 4 p r o v i d e s v e r y h i g h e f f i c i e n c y o v e r l i g h t t o h e a v y l o a d s w i t h l o a d i n g - m o d u l a t e d s w i t c h i n g f r e q u e n c i e s . i n p w m m o d e , t h e c o n - v e r t e r w o r k s n e a r l y a t c o n s t a n t f r e q u e n c y f o r l o w - n o i s e r e q u i r e m e n t s . t h e u n i q u e u l t r a s o n i c m o d e m a i n t a i n s t h e s w i t c h i n g f r e q u e n c y a b o v e 3 7 k h z , w h i c h e l i m i n a t e s n o i s e i n a u d i o a p p l i c a t i o n . a p w 8 7 2 4 i s b u i l t i n r e m o t e s e n s e f u n c t i o n f o r a p p l i c a t i o n s t h a t r e q u i r e r e m o t e s e n s e . t h e a p w 8 7 2 4 i s e q u i p p e d w i t h a c c u r a t e p o s i t i v e c u r r e n t l i m i t , o u t p u t u n d e r - v o l t a g e , a n d o u t p u t o v e r - v o l t a g e p r o t e c t i o n s , p e r f e c t f o r m u l t i f o r m a p p l i c a t i o n s . t h e p o w e r - o n - r e s e t f u n c t i o n m o n i t o r s t h e v o l t a g e o n v c c t o p r e - v e n t w r o n g o p e r a t i o n d u r i n g p o w e r - o n . t h e a p w 8 7 2 4 h a s a n i n t e r n a l 4 m s d i g i t a l s o f t s t a r t t h a t r a m p s u p t h e o u t p u t v o l t a g e w i t h p r o g r a m m a b l e s l e w r a t e t o r e d u c e t h e s t a r t - u p c u r r e n t . t h e e n a b l e f u n c t i o n c a n l e t u s e r e a s y t o a p p l y a p w 8 7 2 4 . t h e a p w 8 7 2 4 i s a v a i l a b l e i n 1 0 p i n t d f n 3 x 3 p a c k a g e r e s p e c t i v e l y . v out l q 1 q 2 en apw 8724 v in fbrtn pok 5 ~ 12 v phase ugate lgate / ocset r pok vcc s i m p l i f i e d a p p l i c a t i o n c i r c u i t free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 a p w 8 7 2 4 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n = gnd and thermal pad ( connected to gnd plane for better heat dissipation ) lgate / ocset 5 6 vcc 7 fbrtn 8 fb 9 en 10 phase tdfn - 10 3 x 3 ( top view ) boot 1 ugate 2 pok 3 gnd 4 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) - 0.3 ~ 16 v v boot - gnd boot supply voltage (boot to gnd) - 0.3 ~ 44 v v boot boot supply voltage (boot to phase) - 0.3 ~ 16 v v en en to gnd - 0.3 ~ v cc +0.3 v all other pins (pok, fbrtn and f b to gnd) - 0.3~7 v ugate voltage (ugate to phase) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ v boot +0.3 - 0.3 ~ v boot +0.3 v lgate voltage (lgate to gnd) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ v cc +0.3 - 0.3 ~ v cc +0.3 v v phase phase voltage (phase to gnd) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ 3 5 - 0.3 ~ 2 8 v apw 8724 handling code temperature range . package code apw 8724 qb : assembly meterial package code temperature range i : - 40 to 85 o c handling code assembly meterial g : halogen and lead free device : qb tdfn 3 x 3 - 10 tr : tape & reel l : lead free device apw 8724 xxxxx xxxxx - date code free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 a p w 8 7 2 4 t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2) tdfn3x3 - 10 55 c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of package is soldered directly on the pcb. symbol parameter range unit v in converter input voltage 3 ~ 25 v vcc vcc supply voltage 4.5 ~ 13.2 v v out converter output voltage 0.6~5 v i out converter output current 0 ~ 25 a t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) n o t e 3 : r e f e r t o t h e a p p l i c a t i o n c i r c u i t f o r f u r t h e r i n f o r m a t i o n . a b s o l u t e m a x i m u m r a t i n g s ( c o n t . ) ( n o t e 1 ) symbol parameter rating unit t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum soldering temperature, 10 seconds 260 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. e l e c t r i c a l c h a r a c t e r i s t i c s APW8724 symbal parameter test condition min. typ. max. unit reference v oltage reference voltage - 0.6 - v t a = 25 o c - 0.6 - +0.6 % v ref regulation accuracy t a = - 40 o c ~ 85 o c, line / load transient - 1.0 - +1.0 % i fb fb input bias current fb=0.5v - - 1 m a i fbrtn fbrtn leakage current - - 1 m a these specifications apply for ta = -40 o c to +85 o c, unless otherwise stated. all typical specifications ta= +25 o c, v cc = 12v free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 a p w 8 7 2 4 e l e c t r i c a l c h a r a c t e r i s t i c s these specifications apply for ta = -40 o c to +85 o c, unless otherwise stated. all typical specifications ta= +25 o c, v cc = 12v APW8724 symbal parameter test condition min. typ. max. unit supply current i vcc vcc input bias current vcc current, en=5v, vfb=0.7v, phase=0.5v - 2 3 ma i vcc_shd n vcc shutdown current en =gnd, vcc=5v - - 10 m a switching frequency and duty t on pwm on time v in =12v, vout=1v 222 278 333 ns t on (min) minimum on time - 100 - ns t off (min) minimum off time v fb =0.45v, v phase = - 0.1v 300 400 500 ns minimum ultras onic skip operating frequency 25 37 - khz power on timing maximum current limit setting time r ocset is open - - 500 m s i ocset e arly sourcing timing from por_r to internal sample clock start - 150 - m s d1 only the first pulse delay by ea offset posit ive offset 60mv(typ.), when t ss is about 4ms, the first pulse delays from sample & hold completed - 350 - m s t ss internal s oft s tart t ime v out =0% to v out regulation(95%) - 4 - ms gate driver 5v ug pull - up resistance vcc=5v, boot - ug=1v - 5 - w 12v ug pull - up resistance vcc=12v, boot - ug=1v - 3 - w 5v ug sink resistance vcc=5v, ug - phase=1v - 2 - w 12v ug sink resistance vcc=12v, ug - phase=1v - 1.3 - w 5v l g pull - up resistance vcc=5v, vcc - lg=1v - 5 - w 12v l g pull - up resistance vcc=12v, vcc - lg=1v - 3 - w 5v l g sink resistance vcc=5v, lg - gnd=1v - 2 - w 12v l g sink resistance vcc=12v, lg - gnd=1v - 1.3 - w ug to lg dead time ug falling to lg rising at vcc=5v - 40 - ns ug falling to lg rising at vcc=12v - 20 - ns lg to ug dead time lg falling to ug rising at vcc=5v - 40 - ns lg falling to ug rising at vcc=12v - 20 - ns bootstrap switch v f ron v vcc ? v boot - gnd , i f = 10ma - 0.2 0.4 v i r reverse leakage v boot - gnd = 30v, v phase = 25v, v vcc = 5v - - 0.5 m a free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 a p w 8 7 2 4 e l e c t r i c a l c h a r a c t e r i s t i c s these specifications apply for ta = -40 o c to +85 o c, unless otherwise stated. all typical specifications ta= +25 o c, v cc = 12v APW8724 symbal parameter test condition min. typ. max. unit vcc por threshold v vcc_thr ris ing vcc por threshold voltage 4.25 4.35 4.45 v vcc por hysteresis - 300 - mv control inputs shutdown - - 0.4 en threshold enable 0.83 - - v en le akage en =0v - 0.1 1.0 m a power - ok indicator pok in from lower (pok goes high) 87 90 93 % pok out from normal falling (pok goes low) 65 70 75 % v pok pok threshold pok out from normal rising (pok goes low) 120 125 130 % i pok p ok leakage current v pok =5v - 0.1 1 m a p ok s ink current v pok =0.5v 5 15 - ma pok enable delay time v out from 0% to pok high - 5.5 - ms current sense i ocset i ocset ocp threshold i ocset sourc ing 22.5 25 27.5 m a t ci ocset i ocset t emperature c oefficient on t he b asis of 25c - 2780 - ppm/ o c v r ocset maximum current l imit t hreshold r ocset open 360 400 440 mv zero c rossing c omparator o ffset v gnd - phase voltage - 3 0 3 mv protection v uv uvp threshold 65 70 75 % uvp debounce interval - 30 - m s uvp enable delay v out from 0% to uvp enable - 5.5 ms v ovr ovp rising threshold v fb rising, lg fully turn on 120 125 130 % ovp fall ing threshold v fb falling, driver both off - 105 - % ovp propagation delay v fb rising - 2 - m s t otr otp rising threshold (note 4) - 150 - o c otp hyste r esis (note 4) - 25 - o c free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 6 a p w 8 7 2 4 p i n d e s c r i p t i o n pin no. name function 1 boot supply input for t he ug ate driver a nd a n i nternal l evel - shift c ircuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. 2 ugate output of t he h igh - side mosfet d r iver. connect this pin to gate of the high - side mosfet. 3 pok power good output. po k i s a n o pen d rain o utput used to in dicate the status of the output voltage. connect the pok in to +5v through a pull - high resistor. 4 gnd signal g round for t he ic 5 lgat e/ocset output of t he l ow - side mosfet d river a nd current - limit setting input. connect this pin to gate of the low - side mosfet. there is an internal source current 25 m a through a resistor from lgate/ocset pin to gnd before power on. this action is used to m onitor the voltage drop across the drain and source of the low - side mo sfet for current limit. 6 vcc supply v oltage i nput p in for c ontrol c ircuitry. connect +5v~+12v from the vcc pin to the gnd. decoupling at least 1f of a mlcc capacitor from the vcc pin to the gnd. 7 fbrtn this pin is the negative node of the differential remote voltage sensing. the rtn pin should be connected to the remote gnd sense point directly. 8 fb output v oltage f eedback p in. t his pin is connected to the resistive divider in remo te side that set the desired output voltage. the p ok , uvp, and ovp circuits detect this signal to report output voltage status. 9 en enable/shutdown pin . when en=1, enable t he pwm c ontroller , en=0, shutdown t he pwm c ontrolle r. 10 phase junction p oint of t he h igh - side mosfet source, o utput f ilter i nductor a nd t he l ow - side mosfet drain. connect this pin to the source of the high - side mosfet. phase serves as the lower supply rail for the u g high - side gate driver. exposed pad gnd signal g round for t he ic free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 7 a p w 8 7 2 4 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 0 . 59 0 . 595 0 . 6 0 . 605 0 . 61 - 20 0 20 40 60 80 100 r e f e r e n c e v o l t a g e ( v ) junction temperature ( o c ) reference voltage vs . junction temperature v cc = 12 v 120 60 65 70 75 80 85 90 0 . 1 1 100 efficiency vs . load current f sw = 300 khz , v out = 1 . 05 v e f f i c i e n c y ( % ) h - side : sm 4370 nskp * 1 l - side : sm 4373 nskp * 1 vin = 19 v vin = 8 v 10 . 0 s w i t c h i n g f r e q u e n c y ( k h z ) 250 260 270 280 290 300 310 320 330 340 350 switching frequency vs . junction temperature - 20 0 20 40 60 80 100 120 junction temperature ( o c ) 3 5 7 9 11 13 15 17 19 21 input voltage ( v ) s w i t c h i n g f r e q u e n c y ( k h z ) ( % ) input voltage vs switching frequency 150 200 250 300 350 400 23 25 vout = 1 . 05 v , iout = 5 a ( pwm ) 0 5 10 15 20 25 1 . 050 1 . 060 1 . 070 1 . 040 input voltage vs output voltage input voltage ( v ) o u t p u t v o l t a g e ( v ) 1 . 030 - 20 0 20 40 60 80 100 120 18 22 24 26 28 30 32 o c s e t c u r r e n t s o u r c e ( u a ) i ocset vs . junction temperature 20 junction temperature ( o c ) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 8 a p w 8 7 2 4 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . ch 1 : v in , 10 v / div ch 2 : vout , 500 mv / div time : 2 ms / div power on 1 3 2 ch 3 : v phase , 10 v / div v in v out v phase ch 2 : vout , 500 mv / div ch 3 : v phase , 10 v / div time : 50 ms / div ch 1 : vin , 10 v / div power off 1 3 2 v in v out v phase enable ch 1 : v en , 5 v / div ch 2 : vout , 500 mv / div time : 1 ms / div ch 3 : v phase , 10 v / div v en v out v phase 1 3 2 shutdown ch 1 : v en , 5 v / div ch 2 : vout , 500 mv / div time : 5 ms / div ch 3 : v phase , 10 v / div ven v out v phase 1 3 2 r load = 12 [ free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 9 a p w 8 7 2 4 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . over - current protection 1 ch 1 : v out , 10 v / div ch 2 : v lgate , 10 v / div time : 20 ms / div 2 r ocset = 5 . 1 k , r ds ( low side ) = 8 . 4 m [ v out i l v lgate ch 3 : v ugate , 20 v / div ch 4 : i l , 10 a / div 3 4 v ugate under - voltage protection ch 1 : v fb , 500 mv / div ch 2 : v lgate , 10 v / div ch 3 : v ugate , 20 v / div time : 10 us / div 1 3 2 v fb v lagte v uagte 2 ch 1 : v out , 500 mv / div ch 2 : v pok , 5 v / div time : 1 ms / div power ok 1 v out p ok 2 1 3 ch 1 : v out , 50 mv / div ch 2 : i out , 5 a / div time : 200 us / div load transient 2 v out i out free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 0 a p w 8 7 2 4 b l o c k d i a g r a m fb error comparator ov uv 70 % v ref 125 % v ref v ref por vcc en digital soft start p w m s i g n a l c o n t r o l l e r v cc boot ugate phase lgate thermal shutdown gnd pok fault latch logic on - time generator v ref x 70 % v ref x 125 % z c phase v cc sample and hold v rocset to lgate 25 m a current limit v rocset sense low - side fbrtn v compare v re f v compare free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 1 a p w 8 7 2 4 t y p i c a l a p p l i c a t i o n c i r c u i t phase fbrtn gnd vcc lgate / ocset apw 8724 ( tdfn 3 * 3 - 10 ) c in 560 f l 1 1 h v in ugate vcc supply 5 v to 12 v boot 6 9 7 5 10 2 1 r vcc 2 r 2 c vcc 1 f q 1 apm 4350 q 2 apm 435 4 c boot 0 . 1 f r ocset fb 8 pok 3 r pok 100 k [ en enable signal 4 r 1 15 k [ v out c out 820 f r 2 10 k [ c out mlcc 22 fx 4 l o a d v + _ near v - _ remote v + _ remote on v - _ near off 5 v pull - high source free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 2 a p w 8 7 2 4 f u n c t i o n d e s c r i p t i o n constant-on-time pwm controller with input feed-for- ward the constant-on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. this ar- chitecture relies on the output filter capacitor?s effective series resistance (esr) to act as a current-sense resis- tor so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time is controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- tional to the input voltage and directly proportional to the output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block. the switching frequency control circuit senses the switch- ing frequency of the high-side switch and keeps regulat- ing it at a constant frequency in pwm mode. the design improves the frequency variation and is more outstand- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. both in pfm and pwm, the on-time generator, which senses input voltage on phase pin, provides very fast on-time response to input line transients. another one-shot sets a minimum off-time (typical: 400ns). the on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. pulse-frequency modulation (pfm) in pfm mode, an automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: in out sw pfm on v v f 1 t = - ultrasonic mode where f sw is the nominal switching frequency of the con- verter in pwm mode. the load current at handoff from pfm to pwm mode is given by: in this case, APW8724 operates in ultrasonic mode with pfm when the load is zero. the ultrasonic mode is illus- trated as below description. the ultrasonic mode activates an unique pfm mode with a minimum switching frequency of 25khz. the minimum frequency 25khz of ultrasonic mode eliminates audio- frequency interference in light load condition. it will transit to unique pfm mode when output loading makes the frequency bigger than ultrasonic frequency. in ultrasonic mode, the controller automatically transits to fixed-frequency pwm operation when the load reaches the same critical conduction point (i load(pfm to pwm) ). when the controller detects that no switching has oc- curred within about 40 m s (typical), an ultrasonic pulse will be occurred. the ultrasonic controller turns on the low-side mosfet firstly to reduce the output voltage. af- ter feedback voltage drops below the internal reference voltage, the controller turns off the low-side mosfet and triggers a constant-on-time. when the constant-on-time has expired, the controller turns on the low-side mosfet again until the inductor current is below the zero-cross- ing threshold. the behavior is the same as pfm mode. in out sw out in pfm on out in ) pfmtopwm ( load v v f 1 l v v t l v v 2 1 i - = - = - power-on-reset (por) a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising por voltage threshold (4.35v, typical), the por signal goes high and the chip initiates soft-start operations. when this voltage drops lower than 4.25v (typical), the por disables the chip. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 3 a p w 8 7 2 4 c u r r e n t - l i m i t t h e c u r r e n t - l i m i t c i r c u i t e m p l o y s a ? v a l l e y ? c u r r e n t - s e n s - i n g a l g o r i t h m ( s e e f i g u r e 1 ) . t h e a p w 8 7 2 4 u s e s t h e l o w - s i d e m o s f e t r d s ( o n ) o f t h e s y n c h r o n o u s r e c t i f i e r a s a c u r r e n t - s e n s i n g e l e m e n t . i f t h e m a g n i t u d e o f t h e c u r r e n t - s e n s e s i g n a l a t p h a s e p i n i s a b o v e t h e c u r r e n t - l i m i t t h r e s h o l d , t h e p w m i s n o t a l l o w e d t o i n i t i a t e a n e w c y c l e . t h e a c t u a l p e a k c u r r e n t i s g r e a t e r t h a n t h e c u r r e n t - l i m i t t h r e s h o l d b y a n a m o u n t e q u a l t o t h e i n d u c t o r r i p p l e c u r r e n t . t h e r e f o r e , t h e e x a c t c u r r e n t - l i m i t c h a r a c t e r i s t i c a n d m a x i - m u m l o a d c a p a b i l i t y a r e t h e f u n c t i o n s o f t h e s e n s e r e s i s t a n c e , i n d u c t o r v a l u e , a n d i n p u t v o l t a g e . figure 1. current-limit algorithm a resistor (r ocset ), connected from the lgate/ocset to gnd, programs the current-limit threshold. before the ic initiates a soft-start process, an internal current source, i ocset (25 m a typical), flowing through the r ocset develops a voltage (v ocset ) across the r ocset . the device holds v ocset and stops the current source, i ocset , during normal operation. the relationship between the sampled volt- age v ocset and the current-limit threshold i limit is given by: i limit can be expressed as i out minus half of peak-to-peak inductor current. the APW8724 has an internal current-limit voltage (v ocset_max ), and the value is 0.4v typically. when the r ocset x i ocset exceeds 0.4v or the r ocset is floating or not connected, the over current threshold will be the internal default value 0.4v. time i n d u c t o r c u r r e n t 0 i peak i out i limit g i u n d e r - v o l t a g e p r o t e c t i o n in the operational process, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- ger than current-limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the fb volt- age after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under- voltage threshold, the under-voltage threshold is 70% of the nominal output voltage, the internal uvp delay counter starts to count. after 30 m s debounce time, the device turns off both high-side and low-side mosefet with latched and starts a soft-stop process to shut down the output gradually. toggling enable pin to low or recycling vcc, will clear the latch and bring the chip back to operation. f u n c t i o n d e s c r i p t i o n ( c o n t . ) ) side low ( r r i 2 ) on ( ds ocset ocset - = limit i the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at phase. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when com- bined with the under-voltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. o v e r - v o l t a g e p r o t e c t i o n ( o v p ) o f t h e p w m c o n v e r t e r t h e o v e r - v o l t a g e p r o t e c t i o n m o n i t o r s t h e f b v o l t a g e t o p r e v e n t t h e o u t p u t f r o m o v e r - v o l t a g e c o n d i t i o n . w h e n t h e o u t p u t v o l t a g e r i s e s a b o v e 1 2 5 % o f t h e n o m i n a l o u t p u t v o l t a g e , t h e a p w 8 7 2 4 t u r n s o f f t h e h i g h - s i d e m o s f e t a n d t u r n s o n t h e l o w - s i d e m o s f e t u n t i l t h e o u t p u t v o l t - a g e f a l l s b e l o w t h e f a l l i n g b e l o w 1 0 5 % , t h e o v p c o m - p a r a t o r i s d i s e n g a g e d a n d b o t h h i g h - s i d e a n d l o w - s i d e d r i v e r s t u r n o f f . t h i s o v p s c h e m e o n l y c l a m p s t h e v o l t a g e o v e r s h o o t a n d d o e s n o t i n v e r t t h e o u t p u t v o l t a g e w h e n o t h e r w i s e a c t i - v a t e d w i t h a c o n t i n u o u s l y h i g h o u t p u t f r o m l o w - s i d e m o s f e t d r i v e r . i t ? s a c o m m o n p r o b l e m f o r o v p s c h e m e s w i t h a l a t c h . o n c e a n o v e r - v o l t a g e f a u l t c o n d i t i o n i s s e t , i t c a n b e r e s e t b y r e l e a s i n g c o m p o r t o g g l i n g v c c p o w e r - o n - r e s e t s i g n a l . free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 4 a p w 8 7 2 4 f u n c t i o n d e s c r i p t i o n ( c o n t . ) e n p i n c o n t r o l when v en is above the en high threshold (0.83v, minimum). th converter is enabled in automatic pfm/ pwm operation mode. when v en is below the en low threshold (0.4v, maximum), the chip is in the shutdown and only low leakage current is taken from vcc. a d a p t i v e s h o o t - t h r o u g h p r o t e c t i o n o f t h e p w m c o n - v e r t e r remote sense APW8724 has a fbrtn pin for applications that require remote sense. in some applications where high current, low voltage and accurate output voltage regulation are needed, fbrtn can sense the negative terminal of re- mote load capacitor directly, and improve output voltage drop which is due to the board interconnection loss. the gate drivers incorporate an adaptive shoot-through protection to prevent high-side and low-side mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off the low-side mosfet, the lgate voltage is monitored until it is below 1.5v threshold, at which time the ugate is released to rise after a constant delay. during turn-off of the high-side mosfet, the ugate-to- phase voltage is also monitored until it is below 1.5v threshold, at which time the lgate is released to rise after a constant delay. power ok indicator the APW8724 features an open-drain pok output pin to indicate one of the ic's working statuses including soft- start, under-voltage fault, over-current fault. in normal operation, when the output voltage rises 90% of its target value, the pok goes high. when the output voltage outruns 50% or 125% of the target voltage, pok signal will be pulled low immediately. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 5 a p w 8 7 2 4 o u t p u t v o l t a g e s e l e c t i o n the output voltage can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier, and the reference voltage is 0.6v. the output voltage is determined by: w h e r e r 1 i s t h e r e s i s t o r c o n n e c t e d f r o m v o u t t o f b a n d r 2 i s t h e r e s i s t o r c o n n e c t e d f r o m f b t o t h e g n d . ? ? ? ? ? + = 2 1 out r r 1 0.6 v a p p l i c a t i o n i n f o r m a t i o n o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t a g e i s f i x e d , i t c a n b e w r i t t e n a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t p u t c a p a c i t o r s e l e c t i o n the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient reponse. higher inductor value reduces the inductor?s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t h o u g h t h e i n d u c t o r v a l u e a n d f r e q u e n c y a r e i n c r e a s e d a n d t h e r i p p l e c u r r e n t a n d v o l t a g e a r e r e d u c e d , a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u - l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this results in a larger output ripple voltage. besides, the inductor needs to have low dcr to reduce the loss of efficiency. o u tp ut voltage ripple and the transient volta ge devia- tion are factors which have to be taken into con sider- ation when selecting an output capacitor. higher capaci- tor value and lower esr reduce the out put ripple and the load transient drop. therefore, selecting high per- formance low esr capacitors is recommended for switching regulator applications. in addition to h igh frequency noise related to mosfet turn-on and turn - o ff, the output voltage ripple includes the capaci tance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor?s current. t h e s e t w o v o l t a g e s c a n b e r e p r e s e n t e d b y : these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. a small decoupling capacitor (1 m f) in parallel for bypass- ing the noise is also recommended, and the voltage rat- ing of the output capacitors are also must be considered. to support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating. i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 6 a p w 8 7 2 4 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) i n p u t c a p a c i t o r s e l e c t i o n ( c o n t . ) m o s f e t s e l e c t i o n t h e a p p l i c a t i o n f o r a n o t e b o o k b a t t e r y w i t h a m a x i m u m v o l t a g e o f 2 4 v , a t l e a s t a m i n i m u m 3 0 v m o s f e t s s h o u l d b e u s e d . t h e d e s i g n h a s t o t r a d e o f f t h e g a t e c h a r g e w i t h t h e r ds(on) o f t h e m o s f e t : t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r a n s f e r c a p a c i - t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) l a y o u t c o n s i d e r a t i o n i n a n y h i g h s w i t c h i n g f r e q u e n c y c o n v e r t e r , a c o r r e c t l a y o u t i s i m p o r t a n t t o e n s u r e p r o p e r o p e r a t i o n o f t h e r e g u l a t o r . w i t h p o w e r d e v i c e s s w i t c h i n g a t h i g h e r f r e q u e n c y , t h e r e s u l t i n g c u r r e n t t r a n s i e n t w i l l c a u s e v o l t a g e s p i k e a c r o s s t h e i n t e r c o n n e c t i n g i m p e d a n c e a n d p a r a s i t i c c i r c u i t e l e m e n t s . a s a n e x a m p l e , c o n s i d e r t h e t u r n - o f f t r a n s i t i o n o f t h e p w m m o s f e t . b e f o r e t u r n - o f f c o n d i t i o n , t h e m o s f e t i s c a r r y i n g t h e f u l l l o a d c u r r e n t . d u r i n g t u r n - o f f , c u r r e n t s t o p s f l o w i n g i n t h e m o s f e t a n d i s f r e e w h e e l i n g b y t h e l o w s i d e m o s f e t a n d p a r a s i t i c d i o d e . a n y p a r a s i t i c i n d u c t a n c e o f t h e c i r c u i t g e n e r a t e s a l a r g e v o l t a g e s p i k e d u r i n g t h e s w i t c h i n g i n t e r v a l . i n g e n e r a l , u s i n g s h o r t a n d w i d e p r i n t e d c i r c u i t t r a c e s s h o u l d m i n i m i z e i n t e r c o n n e c t - i n g i m p e d a n c e s a n d t h e m a g n i t u d e o f v o l t a g e s p i k e . b e s i d e s , s i g n a l a n d p o w e r g r o u n d s a r e t o b e k e p t s e p a - r a t i n g a n d f i n a l l y c o m b i n e d u s i n g g r o u n d p l a n e c o n s t r u c - t i o n o r s i n g l e p o i n t g r o u n d i n g . t h e b e s t t i e - p o i n t b e t w e e n the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. below is a checklist for your layout: f o r t h e l o w - s i d e m o s f e t , b e f o r e i t i s t u r n e d o n , t h e b o d y d i o d e h a s b e e n c o n d u c t i n g . t h e l o w - s i d e m o s f e t d r i v e r w i l l n o t c h a r g e t h e m i l l e r c a p a c i t o r o f t h i s m o s f e t . i n t h e t u r n i n g o f f p r o c e s s o f t h e l o w - s i d e m o s f e t , t h e l o a d c u r r e n t w i l l s h i f t t o t h e b o d y d i o d e f i r s t . t h e h i g h d v / d t o f t h e p h a s e n o d e v o l t a g e w i l l c h a r g e t h e m i l l e r c a p a c i - t o r t h r o u g h t h e l o w - s i d e m o s f e t d r i v e r s i n k i n g c u r r e n t p a t h . t h i s r e s u l t s i n m u c h l e s s s w i t c h i n g l o s s o f t h e l o w - s i d e m o s f e t s . t h e d u t y c y c l e i s o f t e n v e r y s m a l l i n h i g h b a t t e r y v o l t a g e a p p l i c a t i o n s , a n d t h e l o w - s i d e m o s f e t w i l l c o n d u c t m o s t o f t h e s w i t c h i n g c y c l e ; t h e r e f o r e , when using smaller r ds(on) of the low-side mosfet, the con- verter can reduce power loss. t h e g a t e c h a r g e f o r t h i s m o s f e t i s u s u a l l y t h e s e c o n d a r y c o n s i d e r a t i o n . t h e h i g h - s i d e m o s f e t d o e s n o t h a v e t h i s z e r o v o l t a g e s w i t c h - i n g c o n d i t i o n ; i n a d d i t i o n , i t c o n d u c t s f o r l e s s t i m e c o m - p a r e d t o t h e l o w - s i d e m o s f e t , s o t h e s w i t c h i n g l o s s t e n d s t o b e d o m i n a n t . p r i o r i t y s h o u l d b e g i v e n t o t h e m o s f e t s w i t h l e s s g a t e c h a r g e , s o t h a t b o t h t h e g a t e d r i v e r l o s s a n d s w i t c h i n g l o s s w i l l b e m i n i m i z e d . where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high- side mosfet includes an additional transi tion loss. t he switching interval , t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. temperature? curve of the power mosfet. h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r - u p , t h e i n p u t c a p a c i t o r s h a v e t o h a n d l e g r e a t a m o u n t o f s u r g e c u r r e n t . f o r l o w - d u t y n o t e b o o k a p p l i a c t i o n s , c e r a m i c c a p a c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e a d a n c e p c b l a y o u t . k e e p t h e s w i t c h i n g n o d e s ( u g a t e , l g a t e , b o o t , a n d p h a s e ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 7 a p w 8 7 2 4 locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can?t be close to the switching signal traces (ugate, lgate, boot, and phase). a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t c o n s i d e r a t i o n ( c o n t . ) t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t w i t h h i g h p e a k c h a r g i n g a n d d i s c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e a n d l g a t e ) s h o u l d b e s h o r t a n d w i d e . p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e - t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . i n a d d i t i o n , t h e l a r g e l a y o u t p l a n e b e t w e e n t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e n o d e s ) c a n g e t b e t t e r h e a t s i n k i n g . the pgnd is the current sensing circuit reference ground and also the power ground of the lgate low- side mosfet. on the other hand, the pgnd trace should be a separate trace and independently go to the source of the low-side mosfet. besides, the cur- rent sense resistor should be close to ocset pin to avoid parasitic capacitor effect and noise coupling. d e c o u p l i n g c a p a c i t o r s , t h e r e s i s t o r - d i v i d e r , a n d b o o t c a p a c i t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . ) t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i - t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i - t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . p o s s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l l e l w i t h t h e s e s t r a c e s o n a n y l a y e r . recommended minimum footprint 0 . 3 0 mm 1 . 75 mm ground plane for thermalpad thermalvia diameter 12 mil x 5 0 . 27 5 mm 0 . 75 mm 0 . 50 mm tdfn 3 x 3 - 10 l and pattern r ecommendation 2 . 7 0 m m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 8 a p w 8 7 2 4 p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 note : 1. followed from jedec mo-229 veed-5. aaa c nx a3 a1 b a k l e e 2 pin 1 corner d2 pin 1 e d s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 0.70 0.069 0.028 0.002 0.50 bsc 0.016 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 0.08 0.003 aaa free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 9 a p w 8 7 2 4 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d d e v i c e s p e r u n i t package type unit quantity tdfn3x3 - 10 tape & reel 3000 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 0 a p w 8 7 2 4 t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 3 x 3 - 1 0 user direction of feed c l a s s i f i c a t i o n p r o f i l e free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 1 a p w 8 7 2 4 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spe cified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 2 a p w 8 7 2 4 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 free datasheet http:///

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